ACS8530 datasheet(11/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 11

www.semtech.com

ACS8530 SETS

frequency to 8 kHz, the post-division frequency.

(XX = “Leaky Bucket” ID for this input).

(ii) To achieve 8 kHz, the 10 MHz input must be

divided by 1,250. So, if DivN, = 250 = (N+1)

then N must be set to 1,249. This is done by

writing 4E1 hex (1,249 dec to the DivN register

pair Reg. 46/47.

Direct Lock Mode 155 MHz.

The max frequency allowed for phase comparison is

77.76 MHz, so for the special case of a 155 MHz input set

to Direct Lock Mode, there is a divide-by-two function

automatically selected to bring the frequency down to

within the limits of operation.

PECL/LVDS/AMI Input Port Selection

The choice of PECL or LVDS compatibility is programmed

via the cnfg_differential_inputs register, Reg. 36. Unused

PECL differential inputs should be fixed with one input

High (VDD) and the other input Low (GND), or set in LVDS

mode and left floating, in which case one input is

internally pulled High and the other Low.

An AMI port supports a composite clock, consisting of a

64 kHz AMI clock with 8 kHz boundaries marked by

deliberate violations of the AMI coding rules, as specified

in ITU recommendation G.703[6]. Departures from the

nominal pattern are detected within the ACS8530, and

may cause reference-switching if too frequent. See

section DC Characteristics: AMI Input/Output Port, for

more details. If the AMI port is unused, the pins (I1 and I2)

should be tied to GND.

Table 4 Input Reference Source Selection and Priority Table

Port Number

Channel

Number (Bin)

Input Port

Technology

Frequencies Supported

Default

Priority

0001

AMI

64/8 kHz (composite clock, 64 kHz + 8 kHz)

Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz

0010

AMI

64/8 kHz (composite clock, 64 kHz + 8 kHz)

Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz

0011

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 8 kHz Default (SDH): 8 kHz

0100

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 8 kHz Default (SDH): 8 kHz

0101

LVDS/PECL LVDS

default

Up to 155.52 MHz (see Note (ii))