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RC522 Datasheet(PDF) 93 Page - NXP Semiconductors |
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RC522 Datasheet(HTML) 93 Page - NXP Semiconductors |
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93 / 96 page ![]() MFRC522_34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet PUBLIC Rev. 3.4 — 5 March 2010 112134 93 of 96 NXP Semiconductors MFRC522 Contactless reader IC Table 134. AnalogTestReg register bit descriptions . . . . .64 Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation . . . . . . . . . . . . .65 Table 136. TestDAC1Reg register bit descriptions . . . . . .65 Table 137. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation . . . . . . . . . . . . .65 Table 138. TestDAC2Reg register bit descriptions . . . . . .65 Table 139. TestADCReg register (address 3Bh); reset value: xxh bit allocation . . . . . . . . . . . . .65 Table 140. TestADCReg register bit descriptions . . . . . . .65 Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation . . . . . . . . . . . . .66 Table 142. Reserved register bit descriptions . . . . . . . . . .66 Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation . . . . . . . . . . . . .66 Table 144. Reserved register bit descriptions . . . . . . . . . .66 Table 145. Reserved register (address 3Eh); reset value: 03h bit allocation . . . . . . . . . . . . .66 Table 146. Reserved register bit descriptions . . . . . . . . . .66 Table 147. Reserved register (address 3Fh); reset value: 00h bit allocation . . . . . . . . . . . . .66 Table 148. Reserved register bit descriptions . . . . . . . . . .66 Table 149. Command overview . . . . . . . . . . . . . . . . . . . .67 Table 150. Limiting values . . . . . . . . . . . . . . . . . . . . . . . .71 Table 151. Operating conditions . . . . . . . . . . . . . . . . . . . .71 Table 152. Thermal characteristics . . . . . . . . . . . . . . . . . .71 Table 153. Characteristics . . . . . . . . . . . . . . . . . . . . . . . .72 Table 154. SPI timing characteristics . . . . . . . . . . . . . . . .75 Table 155. I2C-bus timing in Fast mode . . . . . . . . . . . . . .76 Table 156. Test bus signals: TestBusSel[4:0] = 07h . . . . .80 Table 157. Test bus signals: TestBusSel[4:0] = 0Dh . . . . .80 Table 158. Test signal descriptions . . . . . . . . . . . . . . . . . .80 Table 159. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 160. Revision history . . . . . . . . . . . . . . . . . . . . . . . .88 |
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