AFE4110 datasheet(35/68 Pages) TI

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GND

VCC

sel_timer0_cci2

CxOUT (Apool)

P1_DIR.1

P1_DIR.0

SMCLK

CCI2A

CCI2B

ACTIVATION _CLK

ACLK

SMCLK

LCD_CP_CLK

TIMER_0

CCR2

OUT2 Signal

Set

TA0CCR2

CCIFG

Comparator 2

TA0CCR2

EQU2

Set

TA0CTL

TAIFG

P1_DIR.2

P1_DIR.3

P1_DIR.4

P1_DIR.5

AFE4110

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SLLSE48

– JANUARY 2012

Figure 5. Timer0_CCR2 Block Diagram

Timer1_A3

Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers. AFE4110 Timer-1 has different Clocks Sources and CCx input multiplexing, compared to MSP430x5

documentation. Timer-1 Clock sources and the CCx input signals described in this document.

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