AFE4110 datasheet(46/68 Pages) TI

46 / 68 page

AFE4110

SLLSE48

– JANUARY 2012

www.ti.com

ANALOG_LDOCFG: Analog LDO configuration

–

ldo_out_mux

–

cap_sw_general

r-0

rw-0

r-0

rw-0

high_cap_sw

low_cap_sw

ldo_bypass

ldo_pd

–

ldo_trim_bits

rw-0

rw-1

r-0

rw-0

ldo_trim_bits

Bits 0-2

LDO voltage trimming (see table below)

ldo_pd

Bit 4

"1" LDO Shut down. Vout=open

ldo_bypass

Bits 5

"1" Bypass the LDO, shorts LDO Vout to VDD

low_cap_sw

Bit 6

"1" Connect the low calibration capacitor (20pF)

high_cap_sw

Bit 7

"1" Connect the high calibration capacitor (40pF)

cap_sw_general

Bit 8-9

ldo_out_mux

Bit 12-13

"00" set the LDO output switch to "off". "11" set LDO output switch to "on"

ldo_trim_bits table:

Setting

Vout[V]

000

1.045

001

10.72

010

1.1

011

1.125

100

0.96

101

0.98

110

111

1.02

ANALOG_LDOCTL Analog LDO control

ldo_ctl (cont.)

rw-0

ldo_ctl

a0_port_sel

LDO_IO_sel

rw-0

rw-1

r-0

rw-0

LDO_IO_sel

Bit 0-3

Used to mux the LDO to IOs in the following order:

<0> – port 1.0;

<1> – port 1.1;

<2> – port 1.4;

<3> – port 3.3;

a0_port_sel

Bit 4

Select which IO goes to A0 input of the A-Pool

– ,0. selects port 1.4

ldo_ctl

Bits 5-15

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