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AFE4110 Datasheet(PDF) 18 Page - Texas Instruments |
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AFE4110 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 68 page  AFE4110 SLLSE48 – JANUARY 2012 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh – 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY System Reset WDTIFG(1) Reset 0x0FFFE 14, highest Power-Up External Reset Watchdog System NMI SVMIFG, VMAIFG(1) (Non)maskable 0x0FFFC 13 Vacant memory access User NMI NMIIFG(1) (2) (Non)maskable 0x0FFFA 12 NMI Timer1_A3 TA1CCR0 CCIFG(3) Maskable 0x0FFF8 11 Timer1_A3 TA1CCR1 CCIFG Maskable 0x0FFF6 10 TA1CCR2 CCIFG TA1IFG(1) (3) Watchdog Timer_A Interval Timer Mode WDTIFG Maskable 0x0FFF4 9 A-Pool CxIFG Maskable 0x0FFF2 8 I/O Port P1 P1IFG.0 to P1IFG.6(1) (3) Maskable 0x0FFF0 7 Timer0_A3 TA0CCR0 CCIFG(3) Maskable 0x0FFEE 6 Timer0_A3 TA0CCR1 CCIFG Maskable 0x0FFEC 5 TA0CCR1 CCIFG TA0IFG(1) (3) I/O Port P2 P2IFG.0 to P2IFG.3(1) (3) Maskable 0x0FFEA 4 I/O Port P3 P3IFG.0 to P3IFG.7(1)(3) Maskable 0x0FFE8 3 I/O Port P4 P4IFG.0 to P4IFG.3(1) (3) Maskable 0x0FFE6 2 LCD Controller LCDFRMIFG, Maskable 0x0FFE4 1 LCDBLKOFFIFG, LCDBLKONIFG, LCDNOCAPIFG The Following Interrupts are multiplexed on I/O Port P3 interrupts Activation Sense(4) (5) Muxed with P3.6 Maskable 0x0FFE8 3 CP 1p8 Valid(4) (5) Muxed with P3.7 Maskable 0x0FFE8 3 Activation sleep counter timeout (4) (5) Muxed with P3.4 Maskable 0x0FFE8 3 CP 1p8 comparator out(4)(5) Muxed with P3.5 Maskable 0x0FFE8 3 LCD CP comparator out (4)(5) Muxed with P3.2 Maskable 0x0FFE8 3 APOOL comparator out(4) Muxed with P3.3 Maskable 0x0FFE8 3 (1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) Interrupt flags are located in the module. (4) No additional synchronization mechanisms beyond standard MSP430 interrupt synchronization (5) Interrupt Signal is directly connoted without a de-glitcher mechanism. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :AFE4110 |
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