AFE4110 datasheet(23/68 Pages) TI

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disable_p3_1

MCLK

CPUOFF

Divider

/1/2/4/8/16/32

DIVMx

ACLK

OSCOFF

Divider

/1/2/4/8/16/32

DIVAx

SMCLK

SCG1

Divider

/1/2/4/8/16/32

DIVSx

SELAx

HF – OSC

SCG0

SELMx

LF-OSC/

VLOCLK

SELSx

CLKIN/XIN/P3.0

ACLK enable logic

MCLK enable logic

SMCLK enable logic

VLOCLK

DIVCLK

32KHz

XTAL

XOUT/P3.1

xt_byp

P3IN.4

P3OUT.1

P3REN.1

P3OUT.0

P3REN.0

xt_byp

EN#

PORT_3.0 + PORT_3.1

AFE4110

www.ti.com

SLLSE48

– JANUARY 2012

Oscillator and System Clock

The clock system in the AFE4110 family of devices is supported by the Compact Clock System (CCS) module

that includes an internal 20kHz current controlled low frequency oscillator (LF-OSC), an internal adjustable

(1-5.4MHz) current controlled high frequency oscillator (HF-OSC), a 1KHz ultra low power oscillator for the

activation block, an external clock input from CLKIN, and a 32kHz crystal oscillator. The CCS module is designed

to meet the requirements of both low system cost and low-power consumption. The CCS provides a fast turn-on

of the oscillators in less than 1 ms.

The CCS module provides the following clock signals:

•

Auxiliary clock (ACLK) is software selectable for individual peripheral modules. ACLK is sourced from the

internal LF-OSC, the internal HF-OSC, an external source via CLKIN, or the crystal oscillator.

•

Main clock (MCLK) is the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

•

Sub-Main clock (SMCLK), the subsystem master clock is software selectable by the peripheral modules.

SMCLK can be sourced by same sources made available to ACLK.

•

VLOCLK this is a low frequency clock sourced by LF-OSC that is constantly available.

Figure 1. Block Diagram of Compact Clock System (CCS)

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