AFE4110 datasheet(27/68 Pages) TI

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AFE4110

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SLLSE48

– JANUARY 2012

Activation Block Hardware Status and Control Registers:

The Activation Block hardware registers control the method of entry and exit from deep sleep (LPM5) mode.

Additional features of the Activation Block registers include the following:

•

VBAT Power On Reset (POR) Circuit

– The VBAT POR is designed to reset the Activation block during initial

system power up that is typical of installation of a battery into the final product.

•

4-16bit words (8B) RAM

– This RAM is implemented in hardware registers. The contents of these registers is

cleared at inital system power up by VBAT POR. The fact that these registers are cleared at initial system

power up allow them to be used to determine whether the CPU is being powered up by battery insertion or

exit from LPM5.

•

16bit Sleep Counter

– The Activation block can be configured to exit LPM5 after the number of Activation

clock cycles that are selected. The counter can also be used as a general purpose down counter without

entering LPM5.

•

28bit Shelf Counter

– This counter starts incrementing after the first time the device enters LPM5. After the

first exit from LPM5 this counter stops and its outputs remain static until VBAT power is removed. The intent

is for this counter to record number of Activation clock periods between initial insertion of a battery in to the

final product and the first usage of the final product. In other words, this counter indicates the length of time

that the final product is on the shelf prior to being used by a consumer.

•

ACTIVE Sample Clock

– To minimize the power required for determining transitions on the ACTIVE pad, the

state of the ACTIVE pad is sampled only at intervals which are set by the duty cycle of the ACTIVE Sample

Clock. The period between samples and the duration of the sample interval are configurable.

The Activation Block 'strobe' registers are not memory mapped and require a multi-step procedure for Reads and

Writes of their contents from the CPU. The Activation register strobe refers to the hardware signal used to

capture data into the bank of hardware registers. The strobe number (strobe address) indicates the bank of

16-hardware registers to be accessed. Only 16-bit (word) accesses are supported.

Activation Strobe Register Read Procedure:

The steps to Read a particular Activation strobe register follows:

1. Write the strobe address of the Activation register to be Read to the ACTIVATION_RD_ADDR register

2. Wait 10-MCLK clock cycles for the transfer of selected data to the ACTIVATION_DATAIN register

3. Read to contents of the ACTIVATION_DATAIN register

Activation Strobe Register Write Procedure:

The steps to Write Activation strobe registers follows:

1. Write to data value to be transferred to the Activation hardware register to the ACTIVATION_DATAOUT

2. Wait 10-MCLK clock cycles for data to transfer to the Activation block

3. Write a '1' to the bit corresponding to the Activation hardware register to be written into the

ACTIVATION_STROBES register.

Note: If multiple bits are written in the ACTIVATION_STROBES register, multiple Activation hardware

registers will be written

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