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AFE4110 Datasheet(PDF) 19 Page - Texas Instruments

Part # AFE4110
Description  MIXED SIGNAL MICROCONTROLLER
PDF  68 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE4110 Datasheet(HTML) 19 Page - Texas Instruments

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AFE4110
www.ti.com
SLLSE48
– JANUARY 2012
Special Function Registers (SFRs)
The AFE4110 SFRs are located in the lowest address space and can be accessed via word or byte formats.
Other SFR registers documented in Texas Instruments MSP430x5xx "Compact SYS Module User's Guide"
(SLAU321).
Legend
rw:
Bit can be read and written.
rw-0,1:
Bit can be read and written. It is reset or set by PUC
rw-(0,1):
Bit can be read and written. It is reset or set by POR.
rw-[0,1]:
Bit can be read and written. It is reset or set by BOR.
SFR bit is not present in device
SFRIE1, SFRIE1_L, SFRIE1_H, Interrupt Enable Register
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
SVMIE
r0
r0
r0
r0
r0
r0
r0
rw-0
7
6
5
4
3
2
1
0
JMBOUTIE
JMBINIE
–
NMIIE
VMAIE
–
OFIE
WDTIE
rw-0
rw-0
r0
rw-0
rw-0
r0
rw-0
rw-0
Reserved
Bits 15
– 9
Reserved. Read back as 0
SVMIE
Bit 8
SVM interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
JMBOUTIE
Bit 7
JTAG mailbox output interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
JMBINIE
Bit 6
JTAG mailbox input interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
Reserved
Bit 5
Reserved. Reads back as 0
NMIIE
Bit 4
NMI pin interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
VMAIE
Bit 3
Vacant memory access interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
Reserved
Bit 2
Reserved. Reads back as 0
OFIE
Bit 1
Oscillator fault interrupt enable flag. 0 interrupts disabled 1 interrupts enabled
WDTIE
Bit 0
Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is
not necessary to set this bit for watchdog mode. Because other bits in ~IE1 may be used for other
modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than
MOV.B or CLR.B instruction
0 interrupts disabled
1 interrupts enabled
Copyright
© 2012, Texas Instruments Incorporated
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