AFE4110 datasheet(22/68 Pages) TI

22 / 68 page

AFE4110

SLLSE48

– JANUARY 2012

www.ti.com

Start-Up Code (SUC)

The AFE4110A Development Start-Up Code (DSUC) supports system debug via a JTAG connection to an

external emulator. After the release of RST/NMI, the DSUC checks for the presence of a JTAG emulator by

reading the contents of the JTAG Mailbox Register. If the emulation password is present in the JTAG Mailbox,

the DSUC unlocks full access to the on chip emulation features, then enters LPM4 while waiting for to enter the

debug session. If the emulation password is not present in the JTAG Mailbox, the DSUC initiates execution of

the Loader Code.

The AFE4110B Production Start-Up Code (PSUC) also supports system debug via a JTAG connection to an

external emulator. The difference is that the PSUC checks for the contents of the JTAG Mailbox Register for a

confidential password. If the confidential password is present in the JTAG Mailbox, the PSUC unlocks full access

to the on chip emulation features, then enters LPM4 while waiting for to enter the debug session. If the

confidential password is not present in the JTAG Mailbox when RST/NMI is released, the PSUC initates

execution of the custom ROM code.

Loader Code (Loader)

The AFE4110A Loader checks for the presence of an external SPI memory device containing a valid data/code

package. The Loader transfers a validated data/code package into Development RAM. During validation and

transfer, the on chip 1.85V charge pump is enabled to supply power to VDDIO and the external SPI memory

device. (PCB level connections are required.) Once the transfer of the data/code package is complete, the

charge pump is disabled, the AFE4110 registers are returned to their default contents, and execution of the code

loaded in Development RAM is initiated.

RAM Memory

The RAM memory is split into three ranges for different purposes: Application memory, lockable application

memory and calibration memory.

Lockable application memory and calibration memory can be protected against accidental erasure by setting a

dedicated lock bit in the special functions register (System Maintenance Register).

Note: The lockable memory is locked by default after release of RST/NMI or exit from LPM5. The user code must

clear the lock bits in the Special Function Register after release of RST/NMI or exit from LPM5 to enable writing

lockable memory.

Peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide (SLAU208) and the

MSP430x09x Family User's Guide (SLAU321).

Digital I/O

There are 4 I/O ports implemented: P1 (7 I/O lines), P2 (4 I/O lines), P3 (6 I/O lines) and P4 (4 I/O lines)

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All individual I/O bits are independently programmable.

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Any combination of input, output, and interrupt conditions is possible.

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Programmable pullup or pulldown on P1 and P3(0-5) ports.

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Programmable pullup on P2, P4 and P3(6,7) ports.

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External VDD (VDDIO) supply (1.1-3.3V range) to P2, P4 and P3(6,7) ports.

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Edge-selectable interrupt input capability for all ports.

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Read/write access to port-control registers is supported by all instructions.

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Ports can be accessed byte-wise (P1, P2, P3 and P4) or word-wise in pairs (P1/P2 combo).

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