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AFE4110 Datasheet(PDF) 21 Page - Texas Instruments |
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AFE4110 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 68 page ![]() AFE4110 www.ti.com SLLSE48 – JANUARY 2012 SFRRPCR, SFRRPCR_H, SFRRPCR_L, Reset Pin Control Register 15 14 13 12 11 10 9 8 – – – – – – – – r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 – – – – SYSRSTRE SYSRSTUP SYSNMIES SYSNMI r0 r0 r0 r0 r1 r1 r1 rw-0 Reserved Bits 15 –9 Reserved. Read back as 0 SYSRSTRE Bit 3 Reset Pin resistor enable 0 Pullup / pulldown resistor at the RST/NMI pin is disabled 1 Pullup / pulldown resistor at the RST/NMI pin is enabled SYSRSTUP Bit 2 Reset resistor pin pullup / pulldown 0 Pulldown is selected 1 Pullup is selected SYSNMIES Bit 1 NMI edge select. This bit selects the interrupt edge for the NMI interrupt when SYSNMI = 1. Modifying this bit can trigger an NMI. Modify this bit when SYSNMI = 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge SYSNMI Bit 0 NMI select. This bit selects the function for the RST/NMI pin 0 Reset function 1 NMI function Table 4. Memory Organization TYPE AFE4110A (Dev RAM) Type AFE4110B (Custom ROM) Interrupt Vectors RAM 32 B ROM 32 B 0xFFE0(1) – 0xFFFF 0xFFE0(1) – 0xFFFF Development RAM RAM 14KB — — 0xC800 – 0xFFFF Application ROM — — ROM 14KB 0xC800 – 0xFFFF TI Start Up Code (DSUC/PSUC) ROM 2KB ROM 2KB 0xC000 – 0xC7FF 0xC000 – 0xC7FF TI Boot Loader Code ROM 14KB — — 0x1E0 – 0x55FF Application RAM RAM 256B RAM 256B 0x1D00 – 0x1DFF 0x1D00 – 0x1DFF Application LRAM (lockable) RAM 128B RAM 128B 0x1C80 – 0x1CFF 0x1C80 – 0x1CFF Calibration RAM (lockable) RAM 128B RAM 128B 0x1C00 – 0x1C7F 0x1C00 – 0x1C7F Peripherals Registers 4 kB Registers 4 kB 0x0000 – 0x0FFF 0x0000 – 0x0FFF (1) not the whole interrupt vector range of CSYS is used on AFE4110 devices Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link(s) :AFE4110 |
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