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AFE4110 Datasheet(PDF) 28 Page - Texas Instruments

Part # AFE4110
Description  MIXED SIGNAL MICROCONTROLLER
PDF  68 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE4110 Datasheet(HTML) 28 Page - Texas Instruments

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AFE4110
SLLSE48
– JANUARY 2012
www.ti.com
The table below describes the function of the Activation strobe registers.
Table 7. Activation Strobe Register Function Table
data in #
strobe0
strobe1
strobe2
strobe3
strobe4
strobe5
strobe6
strobe 7
data in 0
RAM
RAM
RAM
RAM
sleep
ACTIVE
Res_sel
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 1
RAM
RAM
RAM
RAM
sleep
ACTIVE
PD_sel
ACTCLK_Freq_Sel
<2:0>
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 2
RAM
RAM
RAM
RAM
sleep
ACTIVE
Always_sample
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 3
RAM
RAM
RAM
RAM
sleep
ACTIVE
Inv_mode
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 4
RAM
RAM
RAM
RAM
sleep
ACTIVE
Switch_sample_mode_SW
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 5
RAM
RAM
RAM
RAM
sleep
ACTIVE
Switch_sample_mode
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 6
RAM
RAM
RAM
RAM
sleep
ACTIVE
In_mod_sel
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 7
RAM
RAM
RAM
RAM
sleep
ACTIVE
Sleep_mode_sel
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 8
RAM
RAM
RAM
RAM
sleep
ACTIVE
Reserved
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 9
RAM
RAM
RAM
RAM
sleep
ACTIVE
Sleep_start
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 10
RAM
RAM
RAM
RAM
sleep
ACTIVE
Timer_mode
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 11
RAM
RAM
RAM
RAM
sleep
ACTIVE
Reserved
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 12
RAM
RAM
RAM
RAM
sleep
ACTIVE
Reserved
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Period
data in 13
RAM
RAM
RAM
RAM
sleep
ACTIVE
DISCHRG_Vbat
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Width
data in 14
RAM
RAM
RAM
RAM
sleep
ACTIVE
DISCHRG_VCC
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Width
data in 15
RAM
RAM
RAM
RAM
sleep
ACTIVE
Reserved
Reserved
counter
reg 0
reg 1
reg 2
reg 3
Sample Clk Width
Strobe0 - Strobe3: Activation Block RAM Registers
RAM Reg0 - RAM Reg3 - Bits 15 - 0 - Constantly powered registers for used as RAM (Cleared by assertion of
VBAT POR)
Strobe4: Sleep Counter Register
Sleep_counter - Bits 15 - 0 - Sleep counter output value
Strobe5: ACTIVE Sample Clock Configuration Register
ACTIVE_Sample_Clock_Period - Bits 12 - 0 - Number of ACTCLK cycles per period of the ACTIVE sample
clock
0x0000 sets the sampling period to ~8192ms
0x0001 sets the sampling period to ~1ms...
0x0009 sets the sampling period to ~9ms ...
0x1FFF sets the sampling frequency to ~8192ms
ACTIVE_Sample_Clock_Width - Bits 15 - 13 - Number of ACTCLK half-cycles per sample interval of the
ACTIVE sample clock
Strobe6: LPM5 Configuration Register
Res_sel - Bit 0 - PU/PD Resistor Select
1 - 500K
Ω resister selected
0 - 50K
Ω resister selected
28
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Copyright
© 2012, Texas Instruments Incorporated
Product Folder Link(s) :AFE4110



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