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S25FS256S Datasheet(PDF) 138 Page - SPANSION |
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S25FS256S Datasheet(HTML) 138 Page - SPANSION |
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138 / 154 page  138 S25FS-S Family S25FS-S_00_04 November 6, 2013 Data Sheet (Pre limin ar y) Table 12.5 Configuration Register 1 Non-Volatile (CR1NV) Bits Field Name Function Type Default State Description 7 RFU Reserved for Future Use Non-Volatile 0 Reserved. 6 RFU 0 5 TBPROT_O Configures Start of Block Protection OTP 0 1 = BP starts at bottom (Low address). 0 = BP starts at top (High address). 4 RFU Reserved for Future Use RFU 0 Reserved. 3 BPNV_O Configures BP2-0 in Status Register OTP 0 1 = Volatile. 0 = Non-Volatile. 2 TBPARM_O Configures Parameter Sectors location OTP 0 1 = 4-kB physical sectors at top, (high address). 0 = 4-kB physical sectors at bottom (Low address). RFU in uniform sector configuration. 1 QUAD_NV Quad Non-Volatile Non-Volatile 0 Provides the default state for the QUAD bit. 0 FREEZE_D FREEZE Default Non-Volatile Read Only 0 Provides the default state for the Freeze bit. Not user programmable. Table 12.6 Configuration Register 1 Volatile (CR1V) Bits Field Name Function Type Default State Description 7 RFU Reserved for Future Use Volatile CR1NV Reserved. 6 RFU 5 TBPROT Volatile copy of TBPROT_O Volatile Read Only Not user writable. See CR1NV[5] TBPROT_O. 4 RFU Reserved for Future Use RFU Reserved. 3 BPNV Volatile copy of BPNV_O Volatile Read Only Not user writable. See CR1NV[3] BPNV_O. 2 TBPARM Volatile copy of TBPARM_O Volatile Read Only Not user writable. See CR1NV[2] TBPARM_O. 1 QUAD Quad I/O Mode Volatile 1 = Quad. 0 = Dual or Serial. 0 FREEZE Lock-Down Block Protection until next power cycle Volatile Lock current state of Block Protection control bits, and OTP regions. 1 = Block Protection and OTP locked. 0 = Block Protection and OTP unlocked. Table 12.7 Configuration Register 2 Non-Volatile (CR2NV) Bits Field Name Function Type Default State Description 7 AL_NV Address Length OTP 0 1 = 4-byte address. 0 = 3-byte address. 6 QA_NV QPI 0 1 = Enabled - QPI (4-4-4) protocol in use. 0 = Disabled - Legacy SPI protocols in use, instruction is always serial on SI. 5 IO3R_NV IO3 Reset 0 1 = Enabled - IO3 is used as RESET# input when CS# is high or Quad Mode is disabled CR1V[1]=1. 0 = Disabled - IO3 has no alternate function, hardware reset is disabled. 4 RFU Reserved 0 Reserved For Future Use. 3 RL_NV Read Latency 1 0 to 15 latency (dummy) cycles following read address or continuous mode bits. Note that bit 3 has a default value of 1 and may be programmed one time to 0 but cannot be returned to 1. 2 0 1 0 0 0 |
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