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104

Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.32

LOCK# (Bus Lock)

Output

Summary

The processor asserts LOCK# during a sequence of bus cycles to

ensure that the cycles are completed without allowing other bus

masters to intervene. Locked operations consist of two to five

bus cycles. LOCK# is asserted during the following operations:

An interrupt acknowledge sequence

Descriptor Table accesses

Page Directory and Page Table accesses

XCHG instruction

An instruction with an allowable LOCK prefix

In order to ensure that locked operations appear on the bus and

are visible to the entire system, any data operands addressed

during a locked cycle that reside in the processor’s cache are

flushed and invalidated from the cache prior to the locked

operation. If the cache line is in the modified state, it is written

back and invalidated prior to the locked operation. Likewise,

any data read during a locked operation is not cached.

The processor ensures that LOCK# does not glitch.

Driven and Floated

During a locked cycle, LOCK# is asserted off the same clock

edge on which ADS# is asserted and remains asserted until the

last BRDY# of the last bus cycle is sampled asserted. The

processor negates LOCK# for at least one clock between

consecutive sequences of locked operations to allow the system

logic to arbitrate for the bus.

LOCK# is floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD. When LOCK# is floated due to BOFF#

sampled asserted, the system logic is responsible for preserving

the lock condition while LOCK# is in the high-impedance state.

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