AMD-K6 datasheet(126/346 Pages) AMD

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108

Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.37

PCHK# (Parity Check)

Output

Summary

The processor asserts PCHK# during read cycles if it detects an

even parity error on one or more valid bytes of D[63:0] during a

read cycle. (Even parity means that the total number of 1 bits

within each byte of data and its respective data parity bit is

even.) The processor checks data parity for the data bytes that

are valid, as defined by BE[7:0]#, the byte enables.

PCHK# is always driven but is only asserted for memory and I/O

read bus cy cle s and t h e s e cond cy cle o f an interr upt

acknowledge sequence. PCHK# is not driven during any type of

write cycles or special bus cycles. The processor does not take

an internal exception as the result of detecting a data parity

error, and system logic must respond appropriately to the

assertion of this signal.

The processor ensures that PCHK# does not glitch, enabling the

signal to be used as a clocking source for system logic.

Driven

PCHK# is always driven except in Tri-State Test mode. For each

BRDY# returned to the processor during a read cycle with a

parity error detected on the data bus, PCHK# is asserted for

one clock, one clock edge after BRDY# is sampled asserted.

AMD-K6 Datasheet(PDF) 126 Page - Advanced Micro Devices