AMD-K6 datasheet(129/346 Pages) AMD

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Chapter 5

Signal Descriptions

111

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

5.41

SCYC (Split Cycle)

Output

Summary

The processor asserts SCYC during misaligned, locked transfers

on the D[63:0] data bus. The processor generates additional bus

cycles to complete the transfer of misaligned data.

For purposes of bus cycles, the term aligned means:

Any 1-byte transfers

2-byte and 4-byte transfers that lie within 4-byte address

boundaries

8-byte transfers that lie within 8-byte address boundaries

Driven and Floated

SCYC is asserted off the same clock edge as ADS#, and negated

off the clock edge on which NA# or the last expected BRDY# of

the entire locked sequence is sampled asserted. SCYC is only

valid during locked memory cycles.

SCYC is floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD.

5.42

SMI# (System Management Interrupt)

Input, Internal Pullup

Summary

The assertion of SMI# causes the processor to enter System

Management Mode (SMM). Upon recognizing SMI#, the

processor performs the following actions, in the order shown:

1. Flushes its instruction pipelines

2. Completes all pending and in-progress bus cycles

3. Acknowledges the interrupt by asserting SMIACT# after

sampling EWBE# asserted

4. Saves the internal processor state in SMM memory

5. Disables interrupts by clearing the interrupt flag (IF) in

EFLAGS and disables NMI interrupts

6. Jumps to the entry point of the SMM service routine at the

SMM base physical address which defaults to 0003_8000h in

SMM memory

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