AMD-K6 datasheet(133/346 Pages) AMD

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Chapter 5

Signal Descriptions

115

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

5.49

TRST# (Test Reset)

Input, Internal Pullup

Summary

The assertion of TRST# initializes the Test Access Port (TAP) by

resetting its state machine to the Test-Logic-Reset state. See

“Boundary-Scan Test Access Port (TAP)” on page 205 for details

regarding the operation of the TAP controller.

Sampled

TRST# is a completely asynchronous input that does not

require a minimum setup and hold time relative to TCK. See

Table 54 on page 253 for the minimum pulse width requirement.

5.50

VCC2DET (VCC2 Detect)

Output

Summary

VCC2DET is tied to VSS (logic level 0) to indicate to the system

logic that it must supply the specified processor core voltage to

the VCC2 pins. The VCC2 pins supply voltage to the processor

core, independent of the voltage supplied to the I/O buffers on

the VCC3 pins.

Driven

VCC2DET always equals 0 and is never floated — even during

Tri-State Test mode.

5.51

W/R# (Write/Read)

Output

Summary

The processor drives W/R# to indicate whether it is performing

a write or a read cycle on the bus. In addition, W/R# is used to

define other bus cycles, including interrupt acknowledge and

special cycles (see Table 19 on page 119 for more details).

Driven and Floated

W/R# is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted. W/R# is

driven during memory cycles, I/O cycles, special bus cycles, and

interrupt acknowledge cycles.

W/R# is floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD.

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