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Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

See “System Management Mode (SMM)” on page 193 for more

details regarding SMM.

Sampled

SMI# is sampled and latched as a falling edge-sensitive signal.

SMI# is sampled on every clock edge but is not recognized until

the next instruction boundary. If SMI# is to be recognized on

the instruction boundary associated with a BRDY#, it must be

sampled asserted a minimum of three clock edges before the

BRDY# is sampled asserted. If it is asserted synchronously, it

can be asserted for a minimum of one clock. If it is asserted

asynchronously, it must have been negated for a minimum of

two clocks followed by an assertion of a minimum of two clocks.

A second assertion of SMI# while in SMM is latched but is not

recognized until the SMM service routine is exited.

5.43

SMIACT# (System Management Interrupt Active)

Output

Summary

The processor acknowledges the assertion of SMI# with the

assertion of SMIACT# to indicate that the processor has

entered System Management Mode (SMM). The system logic

can use SMIACT# to enable SMM memory. See “SMI# (System

Management Interrupt)” on page 111 for more details.

See “System Management Mode (SMM)” on page 193 for more

details regarding SMM.

Driven

The processor asserts SMIACT# after the last BRDY# of the last

pending bus cycle is sampled asserted (including all pending

write cycles) and after EWBE# is sampled asserted. SMIACT#

remains asserted until after the last BRDY# of the last pending

bus cycle associated with exiting SMM is sampled asserted.

SMIACT# remains asserted during any flush, internal snoop, or

writeback cycle due to an inquire cycle.

AMD-K6 Datasheet(PDF) 130 Page - Advanced Micro Devices