AMD-K6 datasheet(131/346 Pages) AMD

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Chapter 5

Signal Descriptions

113

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

5.44

STPCLK# (Stop Clock)

Input, Internal Pullup

Summary

The assertion of STPCLK# causes the processor to enter the

Stop Grant state, during which the processor’s internal clock is

stopped. From the Stop G rant state, the processor can

subsequently transition to the Stop Clock state, in which the

bus clock CLK is stopped. Upon recognizing STPCLK#, the

processor performs the following actions, in the order shown:

1. Flushes its instruction pipelines

2. Completes all pending and in-progress bus cycles

3. Acknowledges the STPCLK# assertion by executing a Stop

Grant special bus cycle (see Table 19 on page 119)

4. Stops its internal clock after BRDY# of the Stop Grant

special bus cycle is sampled asserted and after EWBE# is

sampled asserted

5. Enters the Stop Clock state if the system logic stops the bus

clock CLK (optional)

See “Clock Control” on page 223 for more details regarding

clock control.

Sampled

STPCLK# is sampled as a level-sensitive input on every clock

edge but is not recognized until the next instruction boundary.

System logic can drive the signal either synchronously or

asynchronously. If it is asserted asynchronously, it must be

asserted for a minimum pulse width of two clocks.

STPCLK# must remain asserted until recognized, which is

indicated by the completion of the Stop Grant special cycle.

5.45

TCK (Test Clock)

Input, Internal Pullup

Summary

TCK is the clock for boundary-scan testing using the Test

Access Port (TAP). See “Boundary-Scan Test Access Port

(TAP)” on page 205 for details regarding the operation of the

TAP controller.

Sampled

The processor always samples TCK, except while TRST# is

asserted.

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