AMD-K6 datasheet(128/346 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.39

RESET (Reset)

Input

Summary

When the processor samples RESET asserted, it immediately

flushes and initializes all internal resources and its internal

state including its pipelines and caches, the floating-point

state, the MMX state, and all registers, and then the processor

jumps to address FFFF_FFF0h to start instruction execution.

The signals BRDYC# and FLUSH# are sampled during the

falling transition of RESET to select the drive strength of

selected output signals and to invoke the Tri-State Test mode,

respectively. (See these signal descriptions for more details.)

Sampled

RESET is sampled as a level-sensitive input on every clock

edge. System logic can drive the signal either synchronously or

asynchronously.

During the initial power-on reset of the processor, RESET must

remain asserted for a minimum of 1.0 ms after CLK and VCC

reach specification before it is negated.

During a warm reset, while CLK and VCC are within their

specification, RESET must remain asserted for a minimum of

15 clocks prior to its negation.

5.40

RSVD (Reserved)

Summary

Reserved signals are a special class of pins that can be treated

in one of the following ways:

As no-connect (NC) pins, in which case these pins are left

unconnected

As pins connected to the system logic as defined by the

industry-standard Pentium interface (Socket 7)

Any combination of NC and Socket 7 pins

In any case, if the RSVD pins are treated accordingly, the

normal operation of the AMD-K6 processor is not adversely

affected in any manner.

See “Pin Designations” on page 269 for a list of the locations of

the RSVD pins.

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