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Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.34

NA# (Next Address)

Input

Summary

System logic asserts NA# to indicate to the processor that it is

ready to accept another bus cycle pipelined into the previous

bus cycle. ADS#, along with address and status signals, can be

asserted as early as one clock edge after NA# is sampled

asserted if the processor is prepared to start a new cycle.

Because the processor allows a maximum of two cycles to be in

progress at a time, the assertion of NA# is sampled while two

cycles are in progress but ADS# is not asserted until the

completion of the first cycle.

Sampled

NA# is sampled every clock edge during bus cycles, starting one

clock edge after the clock edge that negates ADS#, until the last

expected BRDY# of the last executed cycle is sampled asserted

(with the exception of the clock edge after the clock edge that

negates the ADS# for a second pending cycle). Because the

processor latches NA# when sampled, the system logic only

needs to assert NA# for one clock.

5.35

NMI (Non-Maskable Interrupt)

Input

Summary

When NMI is sampled asserted, the processor jumps to the

interrupt service routine defined by interrupt number 02h.

Unlike the INTR signal, software cannot mask the effect of NMI

if it is sampled asserted by the processor. However, NMI is

temporarily masked upon entering System Management Mode

(SMM). In addition, an interrupt acknowledge cycle is not

executed because the interrupt number is predefined.

If NMI is sampled asserted while the processor is executing the

interrupt service routine for a previous NMI, the subsequent

NMI remains pending until the completion of the execution of

the IRET instruction at the end of the interrupt service routine.

Sampled

NMI is sampled and latched as a rising edge-sensitive signal.

During normal operation, NMI is sampled on every clock edge

but is not recognized until the next instruction boundary. If it is

asserted synchronously, it can be asserted for a minimum of one

clock. If it is asserted asynchronously, it must have been

negated for a minimum of two clocks, followed by an assertion

of a minimum of two clocks.

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