AMD-K6 datasheet(119/346 Pages) AMD

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Chapter 5

Signal Descriptions

101

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Sampled

The processor samples IGNNE # as a level-sensitive input on

every clock edge. The system logic can drive the signal either

sync hr o n ousl y or async h r o nousl y. I f i t is ass e r t ed

asynchronously, it must be asserted for a minimum pulse width

of two clocks.

5.28

INIT (Initialization)

Input

Summary

The assertion of INIT causes the processor to empty its

pipelines, to initialize most of its internal state, and to branch

to address FFFF_FFF0h—the same instruction execution

starting point used after RESET. Unlike RESET, the processor

preserves the contents of its caches, the floating-point state, the

MMX state, Model-Specific Registers, the CD and NW bits of

the CR0 register, and other specific internal resources.

INIT can be used as an accelerator for 80286 code that requires

a reset to exit from Protected mode back to Real mode.

Sampled

INIT is sampled and latched as a rising edge-sensitive signal.

INIT is sampled on every clock edge but is not recognized until

the next instruction boundary. During an I/O write cycle, it must

be sampled asserted a minimum of three clock edges before

BRDY # is sampled asserted if it is to be recognized on the

boundary between the I/O write instruction and the following

instruction.

If INIT is asserted synchronously, it can be asserted for a

minimum of one clock. If it is asserted asynchronously, it must

have been negated for a minimum of two clocks, followed by an

assertion of a minimum of two clocks.

AMD-K6 Datasheet(PDF) 119 Page - Advanced Micro Devices