AMD-K6 datasheet(115/346 Pages) AMD

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Chapter 5

Signal Descriptions

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

5.22

FLUSH# (Cache Flush)

Input

Summary

In response to sampling FLUSH# asserted, the processor writes

back any data cache lines that are in the modified state,

invalidates all lines in the instruction and data caches, and then

executes a flush acknowledge special cycle. (See Table 19 on

page 119 for the bus definition of special cycles.)

In addition, FLUSH # is sampled when RESET is negated to

determine if the processor enters Tri-State Test mode. If

FLUSH # is 0 during the falling transition of RESET, the

processor enters Tri-State Test mode instead of performing the

normal RESET functions.

Sampled

FLUSH # is sampled and latched as a falling edge-sensitive

signal. During normal operation (not RESET), FLUSH # is

sampled on every clock edge but is not recognized until the next

instruction boundary. If FLUSH # is asserted synchronously, it

can be asserted for a minimum of one clock. If FLUSH # is

asserted asynchronously, it must have been negated for a

minimum of two clocks, followed by an assertion of a minimum

of two clocks.

FLUSH# is also sampled during the falling transition of RESET.

If RESET and FLUSH # are driven synchronously, FLUSH # is

sampled on the clock edge prior to the clock edge on which

RESET is sampled negated. If RESET is driven asynchronously,

the minimum setup and hold time for FLUSH#, relative to the

negation of RESET, is two clocks.

AMD-K6 Datasheet(PDF) 115 Page - Advanced Micro Devices