AMD-K6 datasheet(117/346 Pages) AMD

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Chapter 5

Signal Descriptions

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

5.25

HLDA (Hold Acknowledge)

Output

Summary

When HOLD is sampled asserted, the processor completes the

current bus cycles, floats the processor bus, and asserts HLDA

in an acknowledgment that these events have been completed.

The processor does not assert HLDA until the completion of a

locked sequence of cycles. While HLDA is asserted, another bus

master can drive cycles on the bus, including inquire cycles to

the processor. The following signals are floated when HLDA is

asserted: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #,

D[63:0], D/C #, DP[7:0], LOCK #, M/IO #, PCD, PWT, SCYC, and

W/R#.

The processor ensures that HLDA does not glitch.

Driven

HLDA is always driven except in Tri-State Test mode. If a

processor cycle is in progress while HOLD is sampled asserted,

HLDA is asserted one clock edge after the last BRDY # of the

cycle is sampled asserted. If the bus is idle, HLDA is asserted

one clock edge after HOLD is sampled asserted. HLDA is

negated one clock edge after the clock edge on which HOLD is

sampled negated.

The assertion of HLDA is independent of the sampled state of

BOFF#.

The processor floats the bus every clock in which HLDA is

asserted.

5.26

HOLD (Bus Hold Request)

Input

Summary

The system logic can assert HOLD to gain control of the

processor’s bus. When HOLD is sampled asserted, the processor

completes the current bus cycles, floats the processor bus, and

asserts HLDA in an acknowledgment that these events have

been completed.

Sampled

The processor samples HOLD on every clock edge. If a

processor cycle is in progress while HOLD is sampled asserted,

HLDA is asserted one clock edge after the last BRDY # of the

cycle is sampled asserted. If the bus is idle, HLDA is asserted

one clock edge after HOLD is sampled asserted. HOLD is

recognized while INIT and RESET are sampled asserted.

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