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Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.27

IGNNE# (Ignore Numeric Exception)

Input

Summary

IGNNE#, in conjunction with the numeric error (NE) bit in CR0,

is used by the system logic to control the effect of an unmasked

floating-point exception on a previous floating-point instruction

during the execution of a floating-point instruction, MMX

instruction, or the WAIT instruction—hereafter referred to as

the target instruction.

If an unmasked floating-point exception is pending and the

target instruction is considered error-sensitive, then the

relationship between NE and IGNNE# is as follows:

If NE = 0, then:

•

If IGNNE# is sampled asserted, the processor ignores the

floating-point

exception

and

continues

with

the

execution of the target instruction.

•

If IGNNE# is sampled negated, the processor waits until

it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted.

If IGNNE# is sampled asserted while waiting, the

processor ignores the floating-point exception and

continues with the execution of the target instruction.

If INTR, SMI#, NMI, or INIT is sampled asserted while

waiting,

the

processor

handles

its

assertion

appropriately.

If NE = 1, the processor invokes the INT 10h exception

handler.

If an unmasked floating-point exception is pending and the

target instruction is considered error-insensitive, then the

processor ignores the floating-point exception and continues

with the execution of the target instruction.

FERR # is not affected by the state of the NE bit or IGNNE #.

FERR # is always asserted at the instruction boundary of the

target instruction that follows the floating-point instruction

that caused the unmasked floating-point exception.

This signal is provided to allow the system logic to handle

exceptions in a manner consistent with IBM-compatible PC/AT

systems.

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