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Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.21

FERR# (Floating-Point Error)

Output

Summary

The assertion of FERR # indicates the occurrence of an

unmaske d fl oati ng-point ex ception res ulting from the

execution of a floating-point instruction. This signal is provided

to allow the system logic to handle this exception in a manner

consistent with IBM-compatible PC/AT systems. See “Handling

Floating-Point Exceptions” on page 189 for a system logic

implementation that supports floating-point exceptions.

The state of the numeric error (NE) bit in CR0 does not affect

the FERR# signal.

The processor ensures that FERR # does not glitch, enabling the

signal to be used as a clocking source for system logic.

Driven

The processor asserts FERR # on the instruction boundary of

the next floating-point instruction, MMX instruction, or WAIT

instruction that occurs following the floating-point instruction

that caused the unmasked floating-point exception—that is,

FERR # is not asserted at the time the exception occurs. The

IGNNE# signal does not affect the assertion of FERR#.

FERR # is negated during the following conditions:

Following the successful execution of the floating-point

instructions FCLEX, FINIT, FSAVE, and FSTENV

Under certain circumstances, following the successful

execution

the

floating-point

instructions

FLDCW,

FLDENV, and FRSTOR, which load the floating-point status

word or the floating-point control word

Following the falling transition of RESET

FERR # is always driven except in Tri-State Test mode.

See “IGNNE# (Ignore Numeric Exception)” on page 100 for

more details on floating-point exceptions.

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