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UPD17015GS Datasheet(PDF) 38 Page - NEC |
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UPD17015GS Datasheet(HTML) 38 Page - NEC |
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38 / 120 page  38 µPD17015 Caution If a read instruction (such as SKT) is executed for a port register specified as an output port, the contents of the output latch and the read data may differ because the status of the output pin is read as is. 9.2.6 Statuses of the I/O Ports upon Reset (1) At power-on reset All pins are set to input mode. The contents of the output latches are reset to 0. (2) At CE reset All pins are set to input mode. The contents of the output latches are retained. (3) At a clock-stop All pins are set to input mode. The contents of the output latches are retained. (4) In the halt state The previous statuses are retained. 9.3 GENERAL-PURPOSE INPUT PORT (P0B0 to P0B2 pins) 9.3.1 Configuration of the Input Port The configuration of the input port is shown below: • P0B (P0B0 to P0B2 pins) VDD Input latch Port register (1 bit) Write instruction Read instruction Read instruction High on-state resistance 5 5 |
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