UPD17015GS datasheet(89/120 Pages) NEC

89 / 120 page

µPD17015

14.6

DEVICE OPERATION CONTROL BY THE CE PIN

The CE pin controls the following functions by means of the input level and rising edge of a signal received from

the outside:

(1) PLL frequency synthesizer

(2) Clock-stop instruction disable/enable

(3) Device reset

14.6.1

PLL Frequency Synthesizer Operation Control

The PLL frequency synthesizer can operate only when the CE pin is high level.

When the level of the CE pin goes low, the PLL is automatically disabled.

In PLL disabled state, the VCOH, VCOL, or EO pin enters the floating state.

The PLL frequency synthesizer can be disabled by program even when the CE pin is high level.

14.6.2

Clock-Stop Instruction Disable/Enable Control

The clock-stop instruction (“STOP s” instruction) is valid only when the CE pin is low level.

If the CE pin is high level, the clock-stop instruction is executed as a no operation instruction (NOP).

14.6.3

Device Reset

Reset (CE reset) can be applied to the device by raising the CE pin from low level to high level.

Besides CE reset, there is also power-on reset, which is activated when VDD is turned on.

For details, see Chapter 15.

UPD17015GS Datasheet(PDF) 89 Page - NEC