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UPD17015GS Datasheet(PDF) 99 Page - NEC |
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UPD17015GS Datasheet(HTML) 99 Page - NEC |
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99 / 120 page  99 µPD17015 15.4 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When VDD is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 15.4.1 through 15.4.3 describe this reset operation. 15.4.1 When VDD Pin and CE Pin Rise Simultaneously Fig. 15-6 (a) shows the reset operation. Power-on reset starts the program from address 0000H. 15.4.2 When CE Pin Raised in Forced Halt State Caused by Power-On Reset. Fig. 15-6 (b) shows the reset operation. Power-on reset starts the program from address 0000H, as in Section 15.4.1. 15.4.3 When CE Pin Raised After Power-On Reset Fig. 15-6 (c) shows the reset operation. Power-on reset starts the program from address 0000H. CE reset restarts the program from address 0000H at the rising edge of the next BTM0CY flag setting signal. |
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