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UPD17015GS Datasheet(PDF) 55 Page - NEC |
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UPD17015GS Datasheet(HTML) 55 Page - NEC |
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55 / 120 page  55 µPD17015 Fig. 11-4 Relationship between the PLL Data Register and Data Buffers DBF3 DBF2 DBF1 DBF0 0CH 0DH 0EH 0FH b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 PLLR 41H 16 0 | 15 (00FH) 16 (010H) | x | 212–1 (FFFH) 216–1 (FFFH) 0 | 255 (00FFH) 256 (0100H) | x | Name Symbol Address Bit Data Symbol Data buffer Transfer data GET instruction allowed PUT instruction allowed Peripheral register Peripheral address Peripheral hardware PLL data register Valid data PLL frequency synthesizer Sets the division ratio of the PLL frequency synthesizer. Direct division Pulse swallow Not to be set Not to be set Division ratio N:N = x Division ratio N:N = x Don’t care Don’t care Don’t care Don’t care Don’t care Name |
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