UPD17015GS datasheet(90/120 Pages) NEC

90 / 120 page

µPD17015

14.6.4

Signal Input to CE Pin

To prevent erroneous operation by noise, the CE pin does not accept signals with a low or high level width of less

than 140

µs. The level of the signal input to the CE pin can be detected with the CE flag of the CE pin level judge

Fig. 14-5 shows the relationship between input signal and CE flag.

Fig. 14-5 Relationship of Signal Input to CE Pin and CE Flag

CE pin

CE flag

Less than 140 s

140 s

Less than 140 s

140 s

CE reset

PLL operation enabled

STOP s instruction invalid (NOP)

PLL disabled

STOP s instruction valid

PLL disabled

STOP s instruction invalid (NOP)

CE reset is applied in synchronization

with the next setting of the BTM0CY flag.

14.6.5

Organization and Functions of CE Pin Level Judge Register

The CE pin level judge register monitors the CE pin input signal level.

Its organization and functions are shown below.

Fig. 14-6 Configuration of CE Pin Level Judge Register

Flag symbol

6AH

Address

Read/write

Power-on

Clock stop

Detects the level input at the CE pin.

Low level input

High level input

0–

Fixed to 0.

CE pin level

judge register

–

The CE flag also does not change when the CE pin receives signals having a low or high level width of less than

140

µs.

UPD17015GS Datasheet(PDF) 90 Page - NEC

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