UPD17015GS datasheet(86/120 Pages) NEC

86 / 120 page

µPD17015

14.4

DEVICE OPERATION IN THE HALT AND CLOCK-STOP STATES

Table 14-1 shows the operation of the CPU and peripheral hardware in the halt state and clock-stop state.

In the halt state, all the peripheral hardware units continue to operate normally except that they stop executing

instructions.

In the clock-stop state, all the peripheral hardware units stop operating.

In the halt state, the peripheral control register that controls the operating state of the peripheral hardware operates

normally (not initialized). However, when a clock-stop instruction is executed, it is initialized to the specified value.

In short, in the halt state, the operation set in the peripheral control register continues and in the clock-stop state,

the operating state is determined in accordance with the initialized peripheral control register value.

For the peripheral control register value in the clock-stop state, see the relevant items.

A sample program is shown below.

Example

Program that sets the P0A1 and P0A0 pins as output ports and which performs LCD display

HLTBTMR

DAT

0001B

; Symbol definition

XTAL

DAT

0000B

INITFLG

P0ABIO1, P0ABIO0

; 1

SET2

P0A1, P0A0

LCDDATA :

; 2

Process B

; 3

SET1

LCDEN

; LCD display on

;

HALT

HLTKEY

; 5

STOP

XTAL

In the example, 1 outputs high level from the P0A1 and P0A0 pins, 2 sets the display data for the LCD segment

When the HALT instruction is executed at

, LCD display continues turning on, and the halt state is released

when a key input is accepted.

If the STOP instruction of ( is executed instead of the HALT instruction of

, all the flags of the peripheral control

and 3 are initialized. LCD display is terminated and P0A1 and P0A0 pins are made general-

purpose input ports.

UPD17015GS Datasheet(PDF) 86 Page - NEC

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