UPD17015GS datasheet(61/120 Pages) NEC

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µPD17015

11.5

PLL DISABLED STATE

The PLL frequency synthesizer is disabled while the CE pin (pin 13) is low level.

The PLL frequency synthesizer is also disabled when VCOH/VCOL pin disabled is selected by the PLL mode

selection register, even if the CE pin is set to high level.

Table 11-3 shows the state of each block at PLL disabled.

Since the PLL mode selection register is not initialized (previous state is held) at CE reset, it is reset to its previous

state when the CE pin rises to high level after dropping to low level and PLL disabled is set.

Therefore, when PLL disabled must be set at CE reset, the PLL reference clock selection register must be initialized

by program.

At power-on reset, PLL disabled is set.

Table 11-3 Operation of Each Block at PLL Disabled

11.6

PLL FREQUENCY SYNTHESIZER USE

To control the PLL frequency synthesizer, the following data is necessary:

(1) Frequency division method : Direct division (MF), pulse swallow (HF, VHF)

(2) Pins to be used

: VCOL and VCOH pins

(3) Reference frequency

: fr

(4) Division value

: N

Sections 11.6.1 to 11.6.3 describe the PLL data setting method for each division method (MF, HF, or VHF).

11.6.1

Direct Division Method (MF)

(1) Selecting the division method to be used

The direct division method is selected by setting the PLLMD0 or PLLMD1 flag of the PLL mode selection register.

(2) Pins to be used

The VCOL pin becomes available when the direct division method is selected.

(3) Reference frequency fr setting

The reference frequency is set by the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register.

Condition

CE pin = low level

CE pin = high level

Block

(PLL disabled)

(PLLMD = 0000B: VCOH/VCOL pin disabled)

VCOL/VCOH pin

Floating

Programmable divider

Frequency division stopped

Reference frequency generator

Output stopped

Phase comparator

Charge pump

EO pin floated

UPD17015GS Datasheet(PDF) 61 Page - NEC

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