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UPD17015GS Datasheet(PDF) 51 Page - NEC |
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UPD17015GS Datasheet(HTML) 51 Page - NEC |
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51 / 120 page  51 µPD17015 11.2 INPUT SWITCHING BLOCK AND PROGRAMMABLE DIVIDER 11.2.1 Configuration Fig. 11-2 shows the configuration of the input switching block and programmable divider. The input switching block consists of the VCOH and VCOL pins and their input amplifiers. The programmable divider consists of a two-modulus prescaler, swallow counter, programmable counter, and division method selection switches. Fig. 11-2 Input Switching Block and Programmable Divider DBF 16 4 12 VCOH VCOL VHF HF MF MF HF VHF PSC VHF HF MF f N PLLMD0 flag PLLMD1 flag 2-4 decoder PLL data register 12 bits 4 bits 2-modulus prescaler 1/16, 1/17 Swallow counter (4 bits) Programmable counter (12 bits) To -DET φ PLL disable signal |
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