UPD17015GS datasheet(101/120 Pages) NEC

101 / 120 page

101

µPD17015

15.5

POWER FAILURE DETECTION

Power failure detection is used to judge whether the device is reset by turning on VDD or by the CE pin, as shown

in Fig. 15-7.

Since the contents of the data memory, output ports, etc. become “undefined” when VDD is turned on, they are

initialized by power failure detection.

A power failure can be detected by using a power failure detection circuit to detect the BTM0CY flag.

Fig. 15-7 Power Failure Detection Flowchart

Program start

Power

failure detect-

ion

Power failure

No power failure

Data memory,

output port, etc.

initialization

15.5.1

Power Failure Detection Circuit

As shown in Fig. 15-1, the power failure detection circuit consists of a voltage detection circuit and timer carry

disable flip-flop that is reset by the output (power-on clear signal) of the voltage detection circuit, and basic timer 0

carry.

The basic timer 0 carry disable flip-flop is set (1) by the power-on clear signal and is cleared (0) when a BTM0CY

flag read instruction is executed.

When the basic timer 0 carry disable flip-flop is set (1), the BTM0CY flag is not set (1).

That is, when the power-on clear signal is output (at power-on reset), the program starts in the state in which the

BTM0CY flag is reset and the setting disabled state is set until a BTM0CY read instruction is executed thereafter.

Once a BTM0CY read instruction is executed, the BTM0CY flag is set at each rising edge of the BTM0CY flag

set pulse thereafter. When reset is applied to the device, the contents of the BTM0CY flag are monitored. If the

BTM0CY flag has been cleared (0), power-on reset (power failure) is judged and if the BTM0CY flag has been set

(1), CE reset (no power failure) is judged.

Since the voltage that can detect a power failure is the same as the voltage applied by power-on reset, VDD becomes

1.8 V (TA = –10 to +50

°C) at crystal oscillation and clock-stop (see Section 15.2).

Fig. 15-8 shows the BTM0CY flag state transition.

Fig. 15-9 shows timing chart and BTM0CY flag operation specified in Fig. 15-8.

UPD17015GS Datasheet(PDF) 101 Page - NEC