UPD17015GS datasheet(104/120 Pages) NEC

104 / 120 page

104

µPD17015

15.5.2

Cautions at Power Failure Detection with BTM0CY Flag

When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the following points.

(1) Clock updating

When writing a clock program by using basic timer 0, the clock must be updated after a power failure.

This is because the BTM0CY flag is cleared (0) and one clock count is lost by BTM0CY flag reading when a power

failure is detected.

(2) Clock update processing time

When the clock is updated, its processing must end before the next rising edge of the BTM0CY flag set pulse.

This is because if the CE pin rises to high level during clock update processing, the clock update processing will

not be executed up to the end and a CE reset will be applied.

For (1) and (2) above, see Section 10.2.6 (1).

When processing is performed at a power failure, careful attention must be given to the following point.

(3) Power failure detection timing

When clock counting, etc. is performed with the BTM0CY flag, the flag must be read for power-failure detection

before the next rising edge of the BTM0CY flag set pulse, after a program starts from address 0000H.

This is because when the BTM0CY flag set time is set to 125 ms, for instance, and power failure detection is

performed 126 ms after the program starts, one BTM0CY flag is lost.

See Section 10.2.6 (1).

As shown in the example on the next page, power failure detection and initialization must be performed within

the BTM0CY flag set time.

This is because when the CE pin is raised and CE reset is applied during power failure processing and initialization,

these processings are interrupted and a problem may occur.

UPD17015GS Datasheet(PDF) 104 Page - NEC