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WM5102 Datasheet(PDF) 136 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 136 Page - Wolfson Microelectronics plc

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WM5102
Production Data
w
PD, June 2014, Rev 4.2
136
AIF TDM AND TRI-STATE CONTROL
The AIFn output pins are tri-stated when the AIFn_TRI register is set. Note that, when a GPIOn pin is
configured as a GPIO, this pin is not affected by the respective AIFn_TRI register. See “General
Purpose Input / Output” to configure the GPIO pins.
Under default conditions, the AIFnTXDAT output is held at logic 0 when the WM5102 is not
transmitting data (ie. during timeslots that are not enabled for output by the WM5102). When the
AIFnTX_DAT_TRI register is set, the WM5102 tri-states the respective AIFnTXDAT pin when not
transmitting data, allowing other devices to drive the AIFnTXDAT connection.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1281
(0501h)
AIF1 Tx
Pin Ctrl
5
AIF1TX_DAT_TR
I
0
AIF1TXDAT Tri-State Control
0 = Logic 0 during unused timeslots
1 = Tri-stated during unused timeslots
R1283
(0503h)
AIF1 Rate
Ctrl
6
AIF1_TRI
0
AIF1 Audio Interface Tri-State Control
0 = Normal
1 = AIF1 Outputs are tri-stated
Note that the GPIO1 pin is only tri-stated
by this register when it is configured as
AIF1TXLRCLK.
Table 41 AIF1 TDM and Tri-State Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1345
(0541h)
AIF2 Tx
Pin Ctrl
5
AIF2TX_DAT_TR
I
0
AIF2TXDAT Tri-State Control
0 = Logic 0 during unused timeslots
1 = Tri-stated during unused timeslots
R1347
(0543h)
AIF2 Rate
Ctrl
6
AIF2_TRI
0
AIF2 Audio Interface Tri-State Control
0 = Normal
1 = AIF2 Outputs are tri-stated
Note that the GPIO2 pin is only tri-stated
by this register when it is configured as
AIF2TXLRCLK.
Table 42 AIF2 TDM and Tri-State Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1409
(0581h)
AIF3 Tx
Pin Ctrl
5
AIF3TX_DAT_TR
I
0
AIF3TXDAT Tri-State Control
0 = Logic 0 during unused timeslots
1 = Tri-stated during unused timeslots
R1411
(0583h)
AIF3 Rate
Ctrl
6
AIF3_TRI
0
AIF3 Audio Interface Tri-State Control
0 = Normal
1 = AIF3 Outputs are tri-stated
Note that the GPIO3 pin is only tri-stated
by this register when it is configured as
AIF3TXLRCLK.
Table 43 AIF3 TDM and Tri-State Control



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