WM5102 datasheet(212/334 Pages) WOLFSON

212 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

212

INTERRUPTS

The Interrupt Controller has multiple inputs. These include the Jack Detect and GPIO input pins,

DSP_IRQn flags, headphone / accessory detection, FLL / ASRC Lock detection, and Clocking

configuration error indications. Any combination of these inputs can be used to trigger an Interrupt

Request (IRQ) event.

The Interrupt Controller supports two sets of interrupt registers. This allows two separate Interrupt

Request (IRQ) outputs to be generated, and for each IRQ to report a different set of input or status

conditions.

For each Interrupt Request (IRQ1 and IRQ2) output, there is an Interrupt register field associated with

each of the interrupt inputs. These fields are asserted whenever a logic edge is detected on the

respective input. Some inputs are triggered on rising edges only; some are triggered on both edges.

Separate rising and falling interrupt registers are provided for the JD1 and GP5 signals. The Interrupt

in Table 95. The Interrupt flags can be polled at any time, or else in response to the Interrupt Request

(IRQ) output being signalled via the IRQ

¯¯¯ pin or a GPIO pin.

All of the Interrupts are edge-triggered, as noted above. Many of these are triggered on both the rising

and falling edges and, therefore, the Interrupt registers cannot indicate which edge has been

detected. The “Raw Status” fields described in Table 96 provide readback of the current value of the

corresponding inputs to the Interrupt Controller. Note that the status of any GPIO inputs can be read

using the GPn_LVL registers, as described in Table 85.

The UNDERCLOCKED_STS and OVERCLOCKED_STS registers represent the logical ‘OR’ of status

flags from multiple sub-systems. The status bits in registers R3364 to R3366 (see Table 96) provide

readback of these lower-level signals. See “Clocking and Sample Rates” for a description of the

Underclocked and Overclocked Error conditions.

Individual mask bits can enable or disable different functions from the Interrupt controller. The mask

bits are described in Table 94 (for IRQ1) and Table 95 (for IRQ2). Note that a masked interrupt input

will not assert the corresponding interrupt register field, and will not cause the associated Interrupt

Request (IRQ) output to be asserted.

The Interrupt Request (IRQ) outputs represent the logical ‘OR’ of the associated interrupt registers.

(IRQ1 is derived from the _EINT1 registers; IRQ2 is derived from the _EINT2 registers). The Interrupt

respective register bit(s). The Interrupt Request (IRQ) outputs are not reset until each of the

associated interrupts has been reset.

A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled

on each pin using the register bits described in Table 85.

The IRQ outputs can be globally masked using the IM_IRQ1 and IM_IRQ2 register bits. When not

masked, the IRQ status can be read from IRQ1_STS and IRQ2_STS for the respective IRQ outputs.

The IRQ1 output is provided externally on the IRQ

¯¯¯ pin. Under default conditions, this output is ‘Active

Low’. The polarity can be inverted using the IRQ_POL register. The IRQ

¯¯¯ output can be either CMOS

driven or Open Drain; this is selected using the IRQ_OP_CFG register.

The IRQ1 and IRQ2 signals may be output on a GPIO pin - see “General Purpose Input / Output”.

The WM5102 Interrupt Controller circuit is illustrated in Figure 67. (Note that not all interrupt inputs are

shown.) The associated control fields are described in Table 93 to Table 96.

Note that, under default register conditions, the ‘Boot Done’ status is the only un-masked interrupt

source; a falling edge on the IRQ

¯¯¯ pin will indicate completion of the Boot Sequence.

WM5102 Datasheet(PDF) 212 Page - Wolfson Microelectronics plc

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