WM5102 datasheet(209/334 Pages) WOLFSON

209 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

209

CONTROL WRITE SEQUENCER STATUS OUTPUT

GPn_FN = 15h.

The WM5102 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write

operations in response to a simple trigger event. See “Control Write Sequencer” for details of the

Control Write Sequencer.

The WSEQ_BUSY register bit (see Table 116) indicates the status of the Control Write Sequencer.

When WSEQ_BUSY=1, this indicates that one or more Write Sequence operations are in progress or

are queued for sequential execution.

A logic signal from the Write Sequencer function may be output directly on any GPIO pin by setting

the respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a short

pulse duration (approx. 100ns) whenever the Write Sequencer has completed all scheduled

sequences, and there are no more pending operations.

The Write Sequencer status is an input to the Interrupt control circuit. An interrupt event is triggered

on completion of a Control Sequence. The associated interrupt bit is latched once set; it can be polled

at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event

handling.

CONTROL INTERFACE ERROR STATUS OUTPUT

GPn_FN = 16h.

The WM5102 is controlled by writing to registers through a 2-wire (I2C) or 4-wire (SPI) serial control

interface, as described in the “Control Interface” section. The SLIMbus interface also supports

read/write access to the control registers, as described in the “SLIMbus Interface Control” section.

The WM5102 performs automatic checks to confirm if a register access is successful. Register access

will be unsuccessful if an invalid register address is selected. Read/write access to the DSP firmware

memory will be unsuccessful if the associated clocking is not enabled. If an invalid or unsuccessful

The Control Interface Error signal may be output directly on any GPIO pin by setting the respective

GPIO registers as described in “GPIO Control”.

The Control Interface Error signal is an input to the Interrupt Controller circuit. An interrupt event is

triggered on the rising edge of the Control Interface Error signal. The associated interrupt bit is latched

once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more

details of the Interrupt event handling.

SYSTEM CLOCKS ENABLE STATUS OUTPUT

GPn_FN = 4Bh, 4Ch.

The WM5102 requires a system clock (SYSCLK) for its internal functions and to support the

input/output signal paths. The WM5102 can support two independent clock domains, with selected

functions referenced to the ASYNCCLK clock domain. See “Clocking and Sample Rates” for details of

these clocks.

The SYSCLK_ENA and ASYNC_CLK_ENA registers (see Table 100) control the SYSCLK and

ASYNCCLK signals respectively. When ‘0’ is written to these registers, the host processor must wait

until the WM5102 has shut down the associated functions before issuing any other register write

commands.

The SYSCLK Enable and ASYNCCLK Enable status may be output directly on any GPIO pin by

setting the respective GPIO registers as described in “GPIO Control”.

The SYSCLK Enable and ASYNCCLK Enable signals are inputs to the Interrupt Controller circuit. An

interrupt event is triggered when the respective clock functions have been shut down. The associated

interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See

“Interrupts” for more details of the Interrupt event handling.

WM5102 Datasheet(PDF) 209 Page - Wolfson Microelectronics plc

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