WM5102 datasheet(205/334 Pages) WOLFSON

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Production Data

WM5102

PD, June 2014, Rev 4.2

205

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

OPCLK_SEL [2:0]

000

OPCLK Source Frequency

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related SYSCLK rates only (ie.

SAMPLE_RATE_n = 01XXX).

The OPCLK Source Frequency must be

less than or equal to the SYSCLK

frequency.

R330

(014Ah)

Output

async clock

OPCLK_ASYNC_

ENA

OPCLK_ASYNC Enable

0 = Disabled

1 = Enabled

7:3

OPCLK_ASYNC_

DIV [4:0]

00h

OPCLK_ASYNC Divider

00h = Divide by 1

01h = Divide by 1

02h = Divide by 2

03h = Divide by 3

…

1Fh = Divide by 31

2:0

OPCLK_ASYNC_

SEL [2:0]

000

OPCLK_ASYNC Source Frequency

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related ASYNCCLK rates only

(ie. ASYNC_SAMPLE_RATE_n =

01XXX).

The OPCLK_ASYNC Source Frequency

must be less than or equal to the

ASYNCCLK frequency.

Table 89 OPCLK and OPCLK_ASYNC Control

FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT

GPn_FN = 0Ch, 0Dh, 0Fh, 10h.

The WM5102 supports FLL status flags, which may be used to control other events. See “Clocking

and Sample Rates” for more details of the FLL.

The ‘FLL Clock OK’ signals indicate that the respective FLL has started up and is providing an output

clock. The ‘FLL Lock’ signals indicate whether FLL Lock has been achieved.

The FLL Clock OK and FLL Lock signals may be output directly on any GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”.

The FLL Clock OK and FLL Lock signals are inputs to the Interrupt Controller circuit. An interrupt

event is triggered on the rising and falling edges of these signals. The associated interrupt bits are

latched once set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for

more details of the Interrupt event handling.

WM5102 Datasheet(PDF) 205 Page - Wolfson Microelectronics plc

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