WM5102 datasheet(206/334 Pages) WOLFSON

206 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

206

FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT

GPn_FN = 05h, 06h.

Clock outputs derived from the FLLs may be output on any GPIO pin. The GPIO output from each

FLLn (where ‘n’ is 1 or 2) is controlled by the respective FLLn_GPCLK_DIV and FLLn_GPCLK_ENA

registers, as described in Table 90.

It is recommended to disable the clock output (FLLn_GPCLK_ENA=0) before making any change to

the respective FLLn_GPCLK_DIV register.

Note that the FLLn_GPCLK_DIV and FLLn_GPCLK_ENA registers affect the GPIO outputs only; they

do not affect the FLL frequency. The maximum output frequency supported for GPIO output is noted

in the “Electrical Characteristics”.

The Frequency Locked Loop (FLL) Clock outputs may be output directly on any GPIO pin by setting

the respective GPIO registers as described in “GPIO Control”.

See “Clocking and Sample Rates” for more details of the WM5102 system clocking and for details of

how to configure the FLLs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R394

(018Ah)

FLL1 GPIO

Clock

7:1

FLL1_GPCLK_DI

V [6:0]

02h

FLL1 GPIO Clock Divider

00h = Divide by 1

01h = Divide by 1

02h = Divide by 2

03h = Divide by 3

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL1_GPCLK_DIV)

FLL1_GPCLK_EN

FLL1 GPIO Clock Enable

0 = Disabled

1 = Enabled

R426

(01AAh)

FLL2 GPIO

Clock

7:1

FLL2_GPCLK_DI

V [6:0]

02h

FLL2 GPIO Clock Divider

00h = Divide by 1

01h = Divide by 1

02h = Divide by 2

03h = Divide by 3

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL2_GPCLK_DIV)

FLL2_GPCLK_EN

FLL2 GPIO Clock Enable

0 = Disabled

1 = Enabled

Table 90 FLL Clock Output Control

PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT

GPn_FN = 08h, 09h.

The WM5102 incorporates two Pulse Width Modulation (PWM) signal generators which can be

enabled as GPIO outputs. The duty cycle of each PWM signal can be modulated by an audio source,

or can be set to a fixed value using a control register setting.

The Pulse Width Modulation (PWM) outputs may be output directly on any GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”.

See “Digital Core” for details of how to configure the PWM signal generators.

WM5102 Datasheet(PDF) 206 Page - Wolfson Microelectronics plc

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