WM5102 datasheet(207/334 Pages) WOLFSON

207 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

207

HEADPHONE DETECTION STATUS OUTPUT

GPn_FN = 12h.

The WM5102 provides a headphone detection circuit on the HPDETL and HPDETR pins to measure

the impedance of an external load connected to the headphone outputs. See “External Accessory

Detection” for further details.

A logic signal from the headphone detection circuit may be output directly on any GPIO pin by setting

the respective GPIO registers as described in “GPIO Control”. This logic signal is set low when a

Headphone Detect measurement is triggered, and is set high when the Headphone Detect function

has completed. A rising edge indicates completion of a Headphone Detect measurement.

The headphone detection circuit is also an input to the Interrupt control circuit. An interrupt event is

triggered whenever a headphone detection measurement has completed. Note that the HPDET_EINT

flag is also asserted when the headphone detection is initiated. The associated interrupt bit is latched

once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more

details of the Interrupt event handling.

MICROPHONE / ACCESSORY DETECTION STATUS OUTPUT

GPn_FN = 13h.

The WM5102 provides an impedance measurement circuit on the MICDETn pins to detect the

connection of a microphone or other external accessory. See “External Accessory Detection” for

further details.

A logic signal from the microphone detect circuit may be output directly on any GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a pulse

duration of 31

s whenever an accessory insertion, removal or impedance change is detected.

The microphone detection circuit is also an input to the Interrupt control circuit. An interrupt event is

triggered whenever an accessory insertion, removal or impedance change is detected. The

associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ

signal. See “Interrupts” for more details of the Interrupt event handling.

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT

GPn_FN = 1Ah, 1Bh.

The WM5102 maintains a flag indicating the lock status of the Asynchronous Sample Rate Converters

(ASRCs), which may be used to control other events if required. See “Digital Core” for more details of

the ASRCs.

The ASRC Lock signals may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The ASRC Lock signals are inputs to the Interrupt control circuit. An interrupt event is triggered on the

rising and falling edges of the ASRC Lock signals. The associated interrupt bits are latched once set;

they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of

the Interrupt event handling.

WM5102 Datasheet(PDF) 207 Page - Wolfson Microelectronics plc

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