WM5102 datasheet(204/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

204

DSP STATUS FLAG (DSP IRQn) OUTPUT

GPn_FN = 35h, 36h, 45h.

The WM5102 supports two DSP Status flags as outputs from the DSP block. These are configurable

within the DSP to provide external indication of the required function(s). A status flag indicating the

DSP1 RAM status is also supported. See “Digital Core” for more details of the DSP.

The DSP Status and DSP RAM Ready flags may be output directly on any GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”. The DSP Status and DSP RAM Ready

outputs are described in Table 88.

The DSP Status flags are inputs to the Interrupt Controller circuit. An interrupt event is triggered on

the rising edge of the DSP Status (DSP_IRQn) flags or DSP RAM Ready flags. The associated

interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.

See “Interrupts” for more details of the Interrupt event handling.

GPN_FN

DESCRIPTION

COMMENTS

35h

DSP Status (DSP_IRQ1)

External indication of DSP_IRQ1_STS

36h

DSP Status (DSP_IRQ2)

External indication of DSP_IRQ2_STS

45h

DSP1 RAM Ready

Indicates DSP1 RAM Ready status

Table 88 DSP Status and RAM Ready Indications

OPCLK AND OPCLK_ASYNC CLOCK OUTPUT

GPn_FN = 04h, 3Dh.

A clock output (OPCLK) derived from SYSCLK can be output on any GPIO pin. The OPCLK

frequency is controlled by OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled using the

OPCLK_ENA register, as described in Table 89.

A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on any GPIO pin. The

OPCLK_ASYNC frequency is controlled by OPCLK_ASYNC_DIV and OPCLK_ASYNC_SEL. The

OPCLK_ASYNC output is enabled using the OPCLK_ASYNC_ENA register

It is recommended to disable the clock output (OPCLK_ENA=0 or OPCLK_ASYNC_ENA=0) before

making any change to the respective OPCLK_DIV, OPCLK_SEL, OPCLK_ASYNC_DIV or

OPCLK_ASYNC_SEL registers.

The OPCLK or OPCLK_ASYNC Clock outputs can be output directly on any GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”.

Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The

OPCLK_ASYNC source frequency cannot be higher than the ASYNCCLK frequency. The maximum

output frequency supported for GPIO output is noted in the “Electrical Characteristics”.

See “Clocking and Sample Rates” for more details of the system clocks (SYSCLK and ASYNCCLK).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R329

(0149h)

Output

system

clock

OPCLK_ENA

OPCLK Enable

0 = Disabled

1 = Enabled

7:3

OPCLK_DIV [4:0]

00h

OPCLK Divider

00h = Divide by 1

01h = Divide by 1

02h = Divide by 2

03h = Divide by 3

…

1Fh = Divide by 31

WM5102 Datasheet(PDF) 204 Page - Wolfson Microelectronics plc

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