WM5102 datasheet(202/334 Pages) WOLFSON

202 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

202

GPn_FN

DESCRIPTION

COMMENTS

49h

Reserved

4Ah

Reserved

4Bh

SYSCLK_ENA Status

0 = SYSCLK_ENA is enabled

1 = SYSCLK_ENA is disabled

4Ch

ASYNC_CLK_ENA

Status

ASYNC_CLK_ENA Status

0 = ASYNC_CLK_ENA is enabled

1 = ASYNC_CLK_ENA is disabled

Table 86 GPIO Function Select (GPIO1, GPIO2, GPIO3, GPIO4)

GPn_FN

DESCRIPTION

COMMENTS

00h

Reserved

01h

Button detect input / Logic

level output

GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL.

GPn_DIR = 1: Button detect or logic level input.

02h

IRQ1 Output

Interrupt (IRQ1) output

0 = IRQ1 not asserted

1 = IRQ1 asserted

03h

IRQ2 Output

Interrupt (IRQ2) output

0 = IRQ2 not asserted

1 = IRQ2 asserted

04h

OPCLK Clock Output

Configurable clock output derived from SYSCLK

05h

FLL1 Clock

Clock output from FLL1

06h

FLL2 Clock

Clock output from FLL2

07h

Reserved

08h

PWM1 Output

Configurable Pulse Width Modulation output PWM1

09h

PWM2 Output

Configurable Pulse Width Modulation output PWM2

3Dh

OPCLK Async Clock

Output

Configurable clock output derived from ASYNCCLK

Table 87 GPIO Function Select (GPIO5)

DIGITAL AUDIO INTERFACE FUNCTION (AIFnTXLRCLK)

GPn_FN = 00h.

The WM5102 provides three digital audio interfaces (AIF1, AIF2 and AIF3).

Under default conditions, the input (RX) and output (TX) paths of each interface use the respective

AIFnRXLRCLK signal as the frame synchronisation clock. If desired, the output (TX) interface can be

configured to use a separate frame clock, AIFnTXLRCLK, using the AIFnTX_LRCLK_SRC registers

as described in “Digital Audio Interface Control”.

The AIFnTXLRCLK function is selected on the respective GPIO pin by setting the GPIO registers as

described in “GPIO Control”.

WM5102 Datasheet(PDF) 202 Page - Wolfson Microelectronics plc

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