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SC1200 Datasheet(PDF) 48 Page - Texas Instruments

Part # SC1200
Description  Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory
PDF  60 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SC1200 Datasheet(HTML) 48 Page - Texas Instruments

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MSC1200
48
SBAS289E
www.ti.com
ADRESL
The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC
bits 7-0
Results. Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared.
ADC Results Register Middle Byte (ADRESM)
7
6
5
4
3
2
1
0
Reset Value
SFR D9H
LSB
00H
7
6
5
4
3
2
1
0
Reset Value
SFR DAH
00H
ADRESM
The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC
bits 7-0
Results.
ADC Results Register High Byte (ADRESH)
ADRESH
The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC
bits 7-0
Results.
7
6
5
4
3
2
1
0
Reset Value
SFR DBH
MSB
00H
7
6
5
4
3
2
1
0
Reset Value
SFR D8H
0
1
EAI
AI
WDTI
0
0
0
40H
Enable Interrupt Control (EICON)
EAI
Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and
bit 5
identified by SFR registers PAI (SFR A5H), AIE (SFR A6H), and AISTAT (SFR A7H).
0 = Auxiliary Interrupt disabled (default).
1 = Auxiliary Interrupt enabled.
AI
Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine,
bit 4
after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates
an Auxiliary Interrupt, if enabled.
0 = No Auxiliary Interrupt detected (default).
1 = Auxiliary Interrupt detected.
WDTI
Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine.
bit 3
Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The
Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabledin HCR0.
0 = No Watchdog Timer Interrupt Detected (default).
1 = Watchdog Timer Interrupt Detected.
ADC Results Register Low Byte (ADRESL)



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