SC1200 datasheet(20/60 Pages) TI

20 / 60 page

MSC1200

SBAS289E

www.ti.com

DIGITAL BROWNOUT RESET

The Digital Brownout Reset (DBOR) is enabled through

Hardware Configuration Register 1 (HCR1). If the conditions

for proper POR are not met or the device encounters a

brownout condition which does not generate a POR, DBOR

can be used to ensure proper device operation. The DBOR

will hold the state of the device when the power supply drops

below the threshold level programmed in HCR1 and then

generate a reset when the supply rises above the threshold

level. Note that, as the device is released from reset and

program execution begins, the device current consumption

may increase, which can result in a power-supply voltage

drop, which may initiate another brownout condition. Addi-

tionally, the DBOR comparison is done against an analog

reference; therefore, AVDD must be within its valid operating

range for DBOR to function.

The DBOR level should be chosen to match closely with the

application. That is, with a high external clock frequency, the

BOR level should match the minimum operating voltage

range for the device, or improper operation may still occur.

ANALOG LOW VOLTAGE DETECT

The MSC1200 contains an analog low-voltage detect. When

the analog supply drops below the value programmed in

LVDCON (SFR E7H), an interrupt is generated.

POWER-UP—SUPPLY VOLTAGE RAMP RATE

The built-in (on-chip) power-on reset circuitry was designed

to accommodate analog or digital supply ramp rates as slow

as 1V/10ms. To ensure proper operation, the power supply

should ramp monotonically at the specified rate. If DBOR is

enabled, the ramp rate can be slower.

CLOCKS

The MSC1200 can operate in three separate clock modes:

internal oscillator mode (IOM), external clock mode (ECM),

and PLL mode. A block diagram is shown in Figure 11. The

clock mode for the MSC1200 is selected via the CLKSEL bits

in HCR2. IOM is the default mode for the device.

Serial Flash Programming mode uses IO LF mode (the

HCR2 and CLKSEL bits have no effect). Table II shows the

active clock mode for the various startup conditions.

Internal Oscillator

In IOM, the CPU executes either in LF mode (if HCR2,

CLKSEL = 111) or HF mode (if HCR2, CLKSEL = 110).

External Clock

In ECM (HCR2, CLKSEL = 011), the CPU can execute from

an external crystal, external ceramic resonator, external

FIGURE 11. Clock Block Diagram.

100k

Ω

220pF

Ceramic

CAP(1)

STOP

Phase

Detector

XIN

XOUT

Charge

Pump

NOTE: (1) The trace length connecting the CAP pin to the 220pF ceramic capacitor should be as short as possible.

VCO

PLL DAC

PLLDIV

SYSDIV

OSC

PLL/tIOM

SYS

CLK

SELECTED CLOCK MODE (HCR2, CLKCON2:0)

STARTUP CONDITION(1)

ACTIVE CLOCK MODE (fSYS)

External Clock Mode (ECM)

Active Clock Present at XIN

External Clock Mode

No Clock Present at XIN

IO LF Mode

Internal Oscillator Mode (IOM)

IO LF Mode

N/A

IO LF Mode

IO HF Mode

N/A

IO HF Mode

PLL(2)

PLL LF Mode

Active 32.768kHz Clock at XIN

PLL LF Mode

No Clock Present at XIN

Nominal: 50% of IO LF Mode Rate

PLL HF Mode

Active 32.768kHz Clock at XIN

PLL HF Mode

No Clock Present at XIN

Nominal: 50% of IO HF Mode Rate

NOTES: (1) Clock detection is only done at startup; refer to Electrical Characteristics parameter tRFD in Figure B.

(2) PLL operation requires that both AVDD and DVDD are within their specified operating range.

TABLE II. Active Clock Modes.

SC1200 Datasheet(PDF) 20 Page - Texas Instruments

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