SC1200 datasheet(55/60 Pages) TI

55 / 60 page

MSC1200

SBAS289E

www.ti.com

Analog Clock (ACLK)

FREQ6-0

Clock Frequency – 1. This value + 1 divides the system clock to create the ADC clock.

bits 6-0

fACLK =

ACLK

CLK

()

+ 1

, where fCLK =

SYSCLK Divider

OSC

fMOD =

ACLK

ADC Data Rate = fDATA =

Decimation Ratio

MOD

System Reset Register (SRST)

Reset Value

SFR F7H

RSTREQ

00H

Reset Value

SFR F6H

FREQ6

FREQ5

FREQ4

FREQ3

FREQ2

FREQ1

FREQ0

03H

RSTREQ

Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset.

bit 0

PLL7-0

PLL Counter Value Least Significant Bit.

bits 7-0

PLL Frequency = External Crystal Frequency • PLL9:0

Phase Lock Loop High Register (PLLH)

Reset Value

SFR F4H

PLL7

PLL6

PLL5

PLL4

PLL3

PLL2

PLL1

PLL0

C1H

Phase Lock Loop Low Register (PLLL)

Reset Value

SFR F5H

CLKSTAT2

CLKSTAT1

CLKSTAT0

PLLLOCK

PLL9

PLL8

x1H

CLKSTAT2-0 Active Clock Status (read only). Derived from HCR2 setting; refer to Table II.

bits 7-5

000: Reserved

001: Reserved

010: Reserved

011: External Clock Mode

100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status)

101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status)

110: Internal Oscillator High-Frequency (HF) Mode

111: Internal Oscillator Low-Frequency (LF) Mode

PLLLOCK

PLL Lock Status and Status Enable.

bit 4

For Write (PLL Lock Status Enable):

0 = No Effect

1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid).

For Read (PLL Lock Status):

0 = PLL Not Locked (PLL may be inactive; refer to Table II for active clock mode)

1 = PLL Locked (PLL is active clock)

PLL9-8

PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4H)

bits 1-0

SC1200 Datasheet(PDF) 55 Page - Texas Instruments

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