SC1200 datasheet(25/60 Pages) TI

25 / 60 page

MSC1200

SBAS289E

www.ti.com

FIGURE 20. Scratchpad Register Addressing.

Direct

RAM

Bank 3

Bank 2

Bank 1

Bank 0

MSB

LSB

It is important to note that the Flash Memory is readable and

writable (depending on the MXWS bit in the MWS SFR) by

the user through the MOVX instruction when configured as

either Program or Data Memory. This means that the user

may partition the device for maximum Flash Program Memory

size (no Flash Data Memory) and use Flash Program Memory

as Flash Data Memory. This may lead to undesirable behav-

ior if the PC points to an area of Flash Program Memory that

is being used for data storage. Therefore, it is recommended

to use Flash partitioning when Flash Memory is used for data

storage. Flash partitioning prohibits execution of code from

Data Flash Memory. Additionally, the Program Memory erase/

write can be disabled through hardware configuration bits

(HCR0), while still providing access (read/write/erase) to

Data Flash Memory.

The effect of memory mapping on Program and Data Memory

is straightforward. The Program Memory is decreased in size

from the top of Flash Memory. To maintain compatibility with

the MSC121x, the Flash Data Memory maps to addresses

0400H. Therefore, access to Data Memory (through MOVX)

will access Flash Memory for the addresses shown in

Table IV.

Data Memory

The MSC1200 has on-chip Flash Data Memory, which is

readable and writable (depending on Memory Write Select

is mapped into the external Data Memory space, which

requires the use of the MOVX instruction to program. Note

that the page size is 64 bytes for both Program and Data

Memory and the page must be erased before it can be

written.

The Register Map is illustrated in Figure 19. It is entirely

separate from the Program and Data Memory areas men-

tioned before. A separate class of instructions is used to

access the registers. There are 128 register locations. In

practice, the MSC1200 has 128 bytes of Scratchpad RAM

and up to 128 SFRs. Thus, a direct reference to one of the

upper 128 locations will be an SFR access. Direct RAM is

reached at locations 0 to 7FH (0 to 127).

SFRs are accessed directly between 80H and FFH (128 to

255). Scratchpad RAM is available for general-purpose data

storage. It is commonly used in place of off-chip RAM when

the total data contents are small. Within the 128 bytes of

RAM, there are several special-purpose areas.

Bit Addressable Locations

In addition to direct register access, some individual bits are

also accessible. These are individually addressable bits in

both the RAM and SFR area. In the Scratchpad RAM area,

registers 20H to 2FH are bit addressable. This provides 128

(16 • 8) individual bits available to software. A bit access is

distinguished from a full-register access by the type of

instruction. In the SFR area, any register location ending in

a 0H or 8H is bit addressable. Figure 20 shows details of the

on-chip RAM addressing including the locations of individual

RAM bits.

FIGURE 19. Register Map.

255

128

127

Direct

Scratchpad

RAM

Direct

Special Function

Registers

SC1200 Datasheet(PDF) 25 Page - Texas Instruments

SC1200 Datasheet(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL