SC1200 datasheet(15/60 Pages) TI

15 / 60 page

MSC1200

SBAS289E

www.ti.com

FIGURE 3. Comparison of MSC1200 Timing to Standard

8051 Timing.

FIGURE 4. MSC1200 Timing Chain and Clock Control.

ALE

PSEN

Internal

AD0-AD7

Internal

A8-A15

ALE

PSEN

AD0-AD7

PORT 2

CLK

Single-Byte, Single-Cycle

Instruction

Single-Byte, Single-Cycle

Instruction

12 Cycles

4 Cycles

standard 8051 core. This allows the user to run the device at

slower clock speeds, which reduces system noise and power

consumption, but provides greater throughput. This performance

difference can be seen in Figure 3. The timing of software loops

will be faster with the MSC1200. However, the timer/counter

operation of the MSC1200 may be maintained at 12 clocks per

increment or optionally run at 4 clocks per increment.

The MSC1200 also provides dual data pointers (DPTRs).

Furthermore, improvements were made to peripheral fea-

tures that off-load processing from the core and the user, to

further improve efficiency. For instance, a 32-bit accumulator

was added to significantly reduce the processing overhead

for the multiple byte data from the ADC or other sources. This

allows for 24-bit addition and shifting to be accomplished in

a few instruction cycles, compared to hundreds of instruction

cycles through software implementation.

Family Device Compatibility

The hardware functionality and pin configuration across the

MSC1200 family is fully compatible. To the user, the only

difference between family members is the memory configuration.

This makes migration between family members simple. Code

written for the MSC1200Y2 can be executed directly on an

MSC1200Y3. This gives the user the ability to add or subtract

software functions and to freely migrate between family mem-

bers. Thus, the MSC1200 can become a standard device used

across several application platforms.

Family Development Tools

The MSC1200 is fully compatible with the standard 8051

instruction set. This means that the user can develop soft-

ware for the MSC1200 with existing 8051 development tools.

Additionally, a complete, integrated development environ-

ment is provided with each demo board, and third-party

developers also provide support.

Power Down Modes

The MSC1200 can power several of the peripherals and put

the CPU into IDLE. This is accomplished by shutting off the

clocks to those sections, as shown in Figure 4.

USEC

MSECH

HMSEC

MSINT

ACLK

divide

by 64

MSECL

µs

100ms

Flash Write

Timing

Flash Erase

Timing

WDTCON

SECINT

FTCON

[3:0]

FTCON

[7:4]

seconds

interrupt

watchdog

milliseconds

interrupt

ADC Output Rate

ADCON3

ADCON2

Decimation Ratio

SPICON/

I2CCON 9A

SCL/SCK

CLK

SYS

(30

µs to 40µs)

(5ms to 11ms)

PDCON.0

PDCON.1

Modulator Clock

PDCON.2

PDCON.3

IDLE

CPU Clock

Timers 0/1

SYSCLK

ADC Power Down

USART

SC1200 Datasheet(PDF) 15 Page - Texas Instruments

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