SC1200 datasheet(37/60 Pages) TI

37 / 60 page

MSC1200

SBAS289E

www.ti.com

Reset Value

SFR 99H

00H

SBUF0

Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and

bits 7-0

receive buffers are separate registers, but both are addressed at this location.

Serial Data Buffer 0 (SBUF0)

SM0-2

Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit

bits 7-5

in addition to the 8 or 9 data bits.

Reset Value

SFR 98H

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00H

REN_0

Receive Enable. This bit enables/disables the serial Port 0 received shift register.

bit 4

0: Serial Port 0 reception disabled.

1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).

TB8_0

9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.

bit 3

RB8_0

9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes

bit 2

2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.

TI_0

Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted

bit 1

out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end

of the last data bit. This bit must be manually cleared by software.

RI_0

Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In

bit 0

serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample

of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of

RB8_0. This bit must be manually cleared by software.

MODE SM0

SM1

SM2 FUNCTION

LENGTH

PERIOD

Synchronous

8 bits

12 pCLK(1)

Synchronous

8 bits

4 pCLK(1)

Asynchronous

10 bits

Timer 1 Baud Rate Equation

Asynchronous—Valid Stop Required(2)

10 bits

Timer 1 Baud Rate Equation

Asynchronous

11 bits

64 pCLK(1) (SMOD = 0)

32 pCLK(1) (SMOD = 1)

Asynchronous with Multiprocessor Communication

11 bits

64 pCLK(1) (SMOD = 0)

32 pCLK(1) (SMOD = 1)

Asynchronous

11 bits

Timer 1 Baud Rate Equation

Asynchronous with Multiprocessor Communication(3)

11 bits

Timer 1 Baud Rate Equation

NOTES: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) RI_0 will only be activated when a valid stop

is received. (3) RI_0 will not be activated if bit 9 = 0.

Serial Port 0 Control (SCON0)

SC1200 Datasheet(PDF) 37 Page - Texas Instruments

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