SC1200 datasheet(28/60 Pages) TI

28 / 60 page

MSC1200

SBAS289E

www.ti.com

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CADDR 3FH

EPMA

PML

RSL

EBR

EWDR

DFSEL1

DFSEL0

Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA.

To read this register during normal operation, refer to the register descriptions for CADDR and CDATA.

EPMA

Enable Programming Memory Access (Security Bit).

bit 7

0: After reset in programming modes, Flash Memory can only be accessed in UAM mode until a mass erase is done.

1: Fully Accessible (default)

PML

Program Memory Lock (PML has Priority Over RSL).

bit 6

0: Enable all Flash Programming Modes in Program Memory; can be written in UAM.

1: Enable read only for Program Memory; cannot be written in UAM (default).

RSL

Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This

bit 5

will allow Program Memory updates without changing the jumpers for in-circuit code updates or program

development. The code in this boot sector would then provide the monitor and programming routines with the ability

to jump into the main Flash code when programming is finished.

0: Enable Reset Sector Writing

1: Enable Read Only Mode for Reset Sector (4kB) (default)

EBR

Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located

bit 4

in Flash Memory.

0: Disable Internal Boot ROM

1: Enable Internal Boot ROM (default)

EWDR

Enable Watchdog Reset.

bit 3

0: Disable Watchdog Reset

1: Enable Watchdog Reset (default)

DFSEL1-0 Data Flash Memory Size (see Table II).

bits 1-0

00: 4kB Data Flash Memory (MSC1200Y3 Only)

01: 2kB Data Flash Memory

10: 1kB Data Flash Memory

11: No Data Flash Memory (default)

SC1200 Datasheet(PDF) 28 Page - Texas Instruments

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